Field of the Invention
The present invention is directed in general to the field of electronic circuits. In one aspect, the present invention relates to a memory access apparatus and method for accessing memory by generating way hit/miss information from base and offset address components.
Description of the Related Art
Data is stored or read from memory at a memory address that is typically computed by adding a base address to an offset address in order to arrive at an effective address for the data. For example, base+offset addressing is used to address memory within data caches, instruction caches, and table-lookaside-buffers (TLBs) as well as data or instructions within other CPU memory units. With such memories, the base and offset values of the memory address are used to determine if the addressed information is stored in the memory. Typically a TAG memory makes this determination by storing addresses of stored information and comparing a TAG portion of the address to the stored addresses to determine if the stored information is present in the memory. A determination that the stored information is present is typically called a hit, and the processing required to make this determination is generally time-consuming because the memory storing the TAG portions of the addresses must be accessed and then compared. In addition, the addition of the base and offset values typically performed to arrive at the effective address usually takes at least two cycles to access the memory. In the first cycle, the base and offset addresses are added, and in the second cycle, the memory is accessed. Since at least two cycles are used to access the memory in a traditional processor, the cycle immediately following a load instruction cannot use the result of the load operation. This delay is referred to as “load latency.” Load latency is a performance limitation factor in traditional processors. Load latency often manifests itself in a pipelined processor as a load-use penalty with the load results being unavailable for two machine cycles.
Accordingly, a need exists for an improved memory access circuit, system and method that addresses various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.